My Projects

Building innovative solutions at the intersection of hardware and software.

Compressor-Based Dadda Multiplier

March 2025 - April 2025

Designed and implemented an optimized 8×8-bit Dadda multiplier using advanced 4-2 and 3-2 compressor techniques, achieving a 16% speed improvement and an 8% power reduction.

Verilog HDL Xilinx Vivado RTL Design Digital Logic

RISC-V Pipelined Processor

May 2025

Developed a complete RISC-V processor implementation from ALU design to multi-stage pipelining, including hazard handling, instruction decoding and register-file operations.

TL-Verilog RISC-V ISA C

AXI4-Lite Protocol-Based Packet Sorter

June 2025

Designed a packet-sorting system using AXI4-Lite with intelligent classification for 32-bit packets and a dual-FIFO architecture optimized for low-latency operation.

AXI4-Lite RTL Design Verilog HDL FIFO

HDL Bits Solutions 101

Dec 2025 - Present

Designed and implemented various kinds of problems on digital logic circuit design in Verilog HDL, from the HDL Bits site.

Verilog HDL RTL Design Digital Logic