Projects - Kirthana P Rao

Compressor-Based Dadda Multiplier

March 2025 - April 2025

Designed and implemented an optimized 8×8 bit Dadda Multiplier using advanced 4-2 and 3-2 compressor techniques for large-scale multiplier applications, achieving 16% speed improvement and 8% power reduction.

Verilog HDL Xilinx Vivado RTL Design Digital Logic

RISC-V Pipelined Processor

May 2025

Developed a complete RISC-V processor implementation from ALU design to multi-stage pipelining with comprehensive hazard handling, instruction decoding, and register file operations.

TL-Verilog RISC-V ISA C

AXI4-Lite Protocol-Based Packet Sorter

June 2025

Designed a packet sorting system using AXI4-Lite Protocol with intelligent data classification for 32-bit packets, utilizing dual FIFO architecture optimized for low-latency operation.

AXI4-Lite RTL Design Verilog HDL FIFO

Research Intern at TiHAN - IIT Hyderabad

June 2024 - July 2024 | IIT Hyderabad

Worked on developing and training a Machine Learning Model for an ADAS-based Project, achieving over 94% accuracy. Also worked as a Project Intern on Network Handover between Cellular Networks (4G LTE) and Wi-Fi Network, using Bash and OpenAir Interface in Unix CLI.

Communication Protocols Network Handover Machine Learning ADAS Bash

Line-Following Robot

SOLASTA Techno-Cultural Fest 2K24

Designed and built an autonomous line-following robot for the RoboRythm competition, featuring sensor-based navigation and real-time path correction algorithm. Achieved 2nd Runner-up position.

Arduino C++ Embedded Systems Sensor Integration

Digital Systems Prototyping

May 2025 - June 2025 | NIELIT Calicut

Hands-on training in FPGA-based digital system design, RTL synthesis, and hardware prototyping during summer internship, covering the complete RTL to bitstream workflow and multiple digital system implementations.